| | Wednesday, June 12, 2002, 8:30 AM - 10:00 AM | Room: 287
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SESSION 20
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| | Theoretical Foundations of Embedded System Design
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| | Chair: Rajesh Gupta - Univ. of California, Irvine, CA
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| | Organizers: Annette Reutter, Donatella Sciuto
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| | This session presents three formal approaches dealing with performance analysis and refinement transformations in embedded systems design. The first paper introduces formal transformation methods for the refinement of an abstract model into an implementation model. The second paper presents a compositional approach to analyze the timing behavior of complex systems under different scheduling strategies. The final paper shows a new timing generation method for the performance analysis of embedded software.
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| |  20.1 |
Transformation Based Communication and Clock Domain Refinement for System Design
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| | | Speaker(s): | Ingo Sander - Royal Institute of Tech., KISTA, Sweden
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| | | Author(s): | Ingo Sander - Royal Institute of Tech., KISTA, Sweden
Axel Jantsch - Royal Institute of Tech., KISTA, Sweden
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| | 20.2 |
Model Composition for Scheduling Analysis in Platform Design |
| | Speaker(s): | Kai R. Richter - Tech. Univ. of Brauwnschweig, Braunschweig, Germany
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| | Author(s): | Kai R. Richter - Tech. Univ. of Brauwnschweig, Braunschweig, Germany
Dirk Ziegenbein - Tech. Univ. of Braunschweig, Braunschweig, Germany
Marek Jersak - Tech. Univ. of Braunschweig, Braunschweig, Germany
Rolf Ernst - Tech. Univ. of Braunschweig, Braunschweig, Germany
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| | 20.3 |
Timed Compiled-Code Simulation of Embedded Software for Performance Analysis of SOC Design |
| | Speaker(s): | Jong-Yeol Lee - KAIST, Taejon, Korea
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| | Author(s): | Jong-Yeol Lee - KAIST, Taejon, Korea
In-Cheol Park - KAIST, Taejon, Korea
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